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Verilog::Netlist::Net.3pm
Langue: en
Version: 2009-04-05 (fedora - 06/07/09)
Section: 3 (Bibliothèques de fonctions)
NAME
Verilog::Netlist::Net - Net for a Verilog ModuleSYNOPSIS
use Verilog::Netlist; ... my $net = $module->find_net ('signalname'); print $net->name;
DESCRIPTION
A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration, and parameter in the current module.ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods.- $self->array
- Any array (vector) declaration for the net. This is for multidimensional signals, for the width of a signal, use msb/lsb/width.
- $self->comment
- Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
- $self->module
- Reference to the Verilog::Netlist::Module the net is in.
- $self->lsb
- The least significant bit number of the net.
- $self->msb
- The most significant bit number of the net.
- $self->name
- The name of the net.
- $self->type
- The C++ or declaration type of the net. For example ``wire'' or ``parameter''.
- $self->value
- If the net's type is 'parameter', the value from the parameter's declaration.
- $self->width
- The width of the net in bits.
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods.- $self->lint
- Checks the net for errors. Normally called by Verilog::Netlist::lint.
- $self->dump
- Prints debugging information for this net.
- $self->dump_drivers
- Prints debugging information for this net, and all pins driving the net.
DISTRIBUTION
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <http://www.veripool.org/verilog-perl>.Copyright 2000-2009 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>SEE ALSO
Verilog-Perl, Verilog::Netlist::Subclass Verilog::NetlistContenus ©2006-2024 Benjamin Poulain
Design ©2006-2024 Maxime Vantorre